Serial data communications are used to communicate data between various devices. Receiving and correctly decoding a stream of serial data requires the system, including a transmitting device and a receiving device (such as a video display), to be synchronized. Often, a source clock signal, e.g., a Link Symbol Clock with a frequency of either 162 MHz (“reduced bit rate”) or 270 MHz (“high bit rate”), and time stamp information or “counters” (also referred to herein as “M” and “N”), are included in a stream of serial data transmitted to the receiving device. In these types of systems, an output clock such as a stream clock (also sometimes referred to as a “pixel clock”) having an output clock frequency that is different than the source clock frequency, e.g., within the range of between 25.175 MHz (such as VGA) and 268.5 MHz (such as WQXGA) at the receiving device must be accurately recovered to increase proper functioning of the system. In certain systems, the M and N time stamp information is embedded in a data stream from the transmitting device, and relates to the relative frequencies between the source clock and the output clock.
However, because of the frequency disparity between the source clock and the output clock, accurate output clock recovery, also sometimes referred to as stream clock recovery (“SCR”), can be difficult with conventional systems. In many systems, a line buffer (also sometimes referred to as a “first in, first out” or “FIFO” buffer) is used to temporarily store and regulate the flow of output clock data, such as pixel data, within the receiving device.
In some systems, the receiving device can perform output clock recovery techniques using a feedback loop, such as a phase-locked loop (“PLL”). The PLL analyzes the serial data stream and attempts to synchronize the receiving device with the transmitting device. However, it is well-known that PLL can result in random and/or deterministic jitter, which can cause transmission errors. This jitter can be continuously accumulated, which can ultimately impact the amount of pixel data in the FIFO buffer. For example, a gradual increase in pixel data in the FIFO buffer can lead to an excess of such data, which is referred to herein as an “overflow” condition. Conversely, a gradual decrease in pixel data in the FIFO buffer can result in a shortage of such data, which is referred to herein as an “underflow” condition. In either the overflow or the underflow condition, frame recovery and/or picture stability of the receiving device can be compromised.